Purushothaman Saravanan

Leading optimization of ML model execution on edge accelerators (NVIDIA Jetson, Qualcomm Hexagon HTP). Key contributions:

• Led end-to-end optimization of an Object Tracker pipeline for HDK 8750, SM 8550 and Jetson Orin; raised throughput 7 → 29 FPS on HTP and ~2× on Jetson via mixed-precision inference.
• Redesigned SAM2 memory-attention by decoupling spatial and temporal features into separate attention paths; fixed RoPE precision bugs, restoring cos-sim > 0.99 vs. FP32 reference.
• Developed PyTorch graph passes replacing NPU-unfriendly layers with HTP-compatible equivalents — e.g., splitting fused QKV into three matmuls to cut DDR round-trips and DMA overhead.
• Designed a half-interleaved RoPE operator to minimize Hexagon HTP DMA transfers; reduced transfer volume by 38% vs. standard interleaved layout.
• Added CUDA Graph execution by automating I/O buffer management across ONNXRuntime and DLTensor; auto-captures static models, cutting YOLO latency ~20%.
• Implemented per-channel INT8 quantization for ONNX → TensorRT with calibration-driven scale clipping; contributed an FP8 bug fix to NVIDIA Model Optimizer.
• Built CI/CD pipeline for automated compiler/runtime validation across 40+ models with accuracy and latency regression checks.

Developed and implemented the NDBlock algorithm for efficient block alignment identification within N-dimensional tensors.

• Demonstrated efficiency through extensive testing on diverse tensors with varying sparsity rates.
• Incorporated OpenMP for parallelization, achieving up to 15× speedup for tensors with modes ≥ 5.

MLIR · Torch-MLIR · LLVM

Built a compiler pipeline lowering PyTorch models through Torch-MLIR with custom passes for operator fusion and constant folding, then targeting TensorRT for hardware-accelerated inference.

• Analyzed IR transformations across Torch dialect, Linalg dialect, and LLVM lowering stages.
• Implemented custom dialect passes for fusion and constant folding.

CUDA · TensorRT

Open-sourced custom TensorRT operator plugins for optimized neural network inference.

• CosLU Plugin: Implemented the Cosine Linear Unit (CosLU) activation function, integrated with trtexec for benchmarking.

PyTorch · ONNX · TensorRT · Nsight

Optimized PIDNet semantic segmentation by converting PyTorch models to ONNX and TensorRT engines.

• Achieved 35% faster inference vs. native PyTorch.
• Profiled GPU workloads with NVIDIA Nsight Systems to identify kernel launch overhead and memory transfer bottlenecks.

Specializing in Machine Learning. CGPA: 4.0/4.0

Relevant courses:

• Neural Networks
• Advanced Machine Learning
• Efficient Tensor Computation for AI
• Compiler Optimization and Scheduling (Audit)
• Computer Vision